MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 980

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Universal Serial Bus Interface
for 3 (transactions) × 1024 (maximum packet size) × 8 (transaction records) = 24576 bytes to be moved
with this data structure, regardless of the alignment offset of the first page.
Since each pointer is a 4K-aligned page pointer, the least-significant 12 bits in several of the page pointers
are used for other purposes.
16-52
31–12
31–12
31–12
31–12
10–0
11–2
11–2
11–8
Bits
Bits
Bits
Bits
1–0
6–0
11
7
Buffer Pointer (Page 0) A 4K-aligned pointer to physical memory. Corresponds to memory address bits 31–12.
Buffer Pointer
Buffer Pointer
Buffer Pointer
Packet Size
Maximum
(Page 1)
Device Address
(Page 2)
Name
Name
Name
I/O
Mult
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
—
Name
EndPt
—
This is a 4K aligned pointer to physical memory. Corresponds to memory address bits 31–12.
Direction (I/O). This field encodes whether the high-speed transaction should use an IN or OUT PID.
0 OUT
1 IN
This directly corresponds to the maximum packet size of the associated endpoint ( wMaxPacketSize ).
This field is used for high-bandwidth endpoints where more than one transaction is issued per
transaction description (for example, per micro-frame). This field is used with the Multi field to support
high-bandwidth pipes. This field is also used for all IN transfers to detect packet babble. Software
should not set a value larger than 1024 (0x400). Any value larger yields undefined results.
This is a 4K-aligned pointer to physical memory. Corresponds to memory address bits 31–12.
Reserved, should be cleared. This bit reserved for future use and should be cleared.
Indicates to the host controller the number of transactions that should be executed per transaction
description (for example, per micro-frame).
00 Reserved, should be cleared. A zero in this field yields undefined results.
01 One transaction to be issued for this endpoint per micro-frame
10 Two transactions to be issued for this endpoint per micro-frame
11 Three transactions to be issued for this endpoint per micro-frame
This is a 4K aligned pointer to physical memory. Corresponds to memory address bits 31–12.
Reserved, should be cleared. These bits reserved for future use and should be cleared.
Selects the particular endpoint number on the device serving as the data source or sink.
Reserved, should be cleared. Reserved for future use and should be initialized by software
to zero.
This field selects the specific device serving as the data source or sink.
Table 16-43. iTD Buffer Pointer Page 1 (Plus)
Table 16-44. Buffer Pointer Page 2 (Plus)
Table 16-42. Buffer Pointer Page 0 (Plus)
Table 16-45. Buffer Pointer Page 3–6
Description
Description
Description
Description
Freescale Semiconductor