MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 598

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

PCI Bus Interface
Table 13-8
13.3.2.2
PCI_ECDR contains fields for controlling the capture of the transaction that caused an error. Each bit
corresponds to the error condition reported in the PCI error status register (PCI_ESR). Note that only the
first error is captured, so disabling the capture of some error types may allow greater visibility of the
significant errors.
Figure 13-6
13-16
Offset 0x04
Reset
27–31
1–20
•
•
Bits
W
R
21
22
23
24
25
26
0
0
1 = Do not capture the transaction that caused this error.
0 = Capture the transaction that caused this error.
describes the bit settings of the PCI_ESR register.
shows the PCI_ECDR fields.
PCISERR PCI system error.Set when the PCI_SERR input signal is asserted. See
MPERR
NORSP
PCI Error Capture Disable Register (PCI_ECDR)
TPERR
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
MERR
Name
APAR
TABT
—
—
Reserved
other than this PCI controller.
information on PCI_SERR.
this PCI controller or when a data parity error is detected by this PCI controller on a read access that
it initiated.
signal is asserted on a read access or a data parity error is detected by this PCI controller on a write
access.
PCI bus (no PCI_DEVSEL assertion).
Reserved
Multiple errors. Set if any other bit of this register is 1 and the same error type occurs again.
Address parity error. Set when there is an address parity error on a PCI access initiated by a device
Master parity error. Set when the PCI_PERR input signal is asserted on a write access initiated by
Target parity error. Set when this PCI controller is the target of a transaction and the PCI_PERR input
No response. Set when there is no response to a transaction initiated by this PCI controller on the
Target abort. Set when a PCI target abort occurs on a transaction initiated by this PCI controller.
Figure 13-6. PCI Error Capture Disable Register (PCI_ECDR)
—
Table 13-8. PCI_ESR Field Descriptions
20
APAR PCISERR
21
All zeros
22
Description
MPERR TPERR NORSP TABT
23
24
25
Table 13-3
Freescale Semiconductor
Access: Read/Write
26
for more
27
—
31