MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 544

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
10.5.4.5
An example of configuring FCM to execute a block erase command to large-page NAND Flash is shown
in
erase status in MDR[AS0]. The sequence is initiated by writing FMR[OP] = 10, and issuing a special
operation to the bank. At the conclusion of the sequence, eLBC will issue a command complete interrupt
(LTESR[CC]) if interrupts are enabled.
Note that operations specified by OP3 and OP4 (status read) should never be skipped while erasing a
NAND Flash device, because, in case that happens, contention may arise on LGPL4. A possible case is
that the next transaction from eLBC may try to use that pin as an output and since the NAND Flash device
might already be driving it, contention will occur. In case OP3 and OP4 operations are skipped, it may also
happen that a new command is issued to the NAND Flash device even when the device has not yet finished
processing the previous request. This may also result in unpredictable behavior.
10.5.4.6
An example of configuring FCM to execute a program command to large-page NAND Flash is shown in
Table
RAM, generating ECC as it proceeds. The shared buffer (buffer 1 for page index 5) must be initialized by
software prior to starting the sequence. The sequence is initiated by writing FMR[OP] = 10, and issuing a
special operation to the bank. At the conclusion of the sequence, eLBC will issue a command complete
interrupt (LTESR[CC]) if interrupts are enabled. The status of the programming operation is returned in
MDR[AS0].
Note that operations specified by OP5 and OP6 (status read) should never be skipped while programming
a NAND Flash device, because, in case that happens, contention may arise on LGPL4. A possible case is
that the next transaction from eLBC may try to use that pin as an output and since the NAND Flash device
might already be driving it, contention will occur. In case OP5 and OP6 operations are skipped, it may also
10-96
Table
10-49. This sequence writes an entire page (main and spare region) from the shared FCM buffer
10-48. This sequence does not require use of the shared FCM buffer RAM, but returns with the
Register
FBAR
FBCR
FPAR
MDR
FCR
FIR
NAND Flash Block Erase Command Sequence Example
NAND Flash Program Command Sequence Example
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 10-48. FCM Register Settings for Block Erase (OR n [PGS] = 1)
(e.g. block 0x00010AB4)
Initial Contents
0x426DB000
0x6070D000
0x00000000
block index
—
—
CMD0 = 0x60 = block address entry;
CMD1 = 0x70 = read status
CMD2 = 0xD0 = erase block;
BLK locates index of 128-Kbyte block
PI = 0 to locate block boundary
unused
returns with AS0 holding erase status
OP0 = CM0 = command 0;
OP1 = PA = page address;
OP2 = CM2 = command 2;
OP3 = CW1 = wait on Flash ready and issue command 1;
OP4 = RS = read erase status into MDR[AS0];
OP5–OP7 = NOP
Description
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