MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 1057

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

It is also not necessary to initially prime Endpoint 0 because the first packet received will always be a setup
packet. The contents of the first setup packet will require a response in accordance with USB device
framework command set.
16.8.2
From a chip or system reset, the USB_DR enters the powered state. A transition from the powered state to
the attach state occurs when the run/stop bit (USBCMD[RS]) is set to a ‘1’. After receiving a reset on the
bus, the port will enter the defaultFS or defaultHS state in accordance with the protocol reset described in
Appendix C.2 of the USB Specification Rev. 2.0. The following state diagram depicts the state of a USB
2.0 device.
Freescale Semiconductor
4. Set CONTROL[USB_EN]
5. Allocate and initialize device queue heads in system memory Minimum: Initialize device queue
6. Configure the ENDPOINTLISTADDR pointer.
7. Enable the microprocessor interrupt associated with the USB DR module and optionally change
8. Set USBCMD[RS] to run mode.
heads 0 Tx and 0 Rx.
For information on device queue heads, refer
For additional information on ENDPOINTLISTADDR, refer to the register table.
setting of USBCMD[ITC].
Recommended: enable all device interrupts including: USBINT, USBERRINT, Port Change
Detect, USB Reset Received, DCSuspend.
For a list of available interrupts refer to the USBINTR and the USBSTS register tables.
After the run bit is set, a device reset will occur. The DCD must monitor the reset event and set the
DEVICEADDR register, set the ENDPTCTRLx registers, and adjust the software state as
described in the Bus Reset section of the following Port State and Control section below.
Port State and Control
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
All device queue heads must be initialized for control endpoints before the
endpoint is enabled. Device queue heads for non-control endpoints must be
initialized before the endpoint can be used.
Endpoint 0 is designed as a control endpoint only and does not need to be
configured using ENDPTCTRL0 register.
NOTE
NOTE
toSection 16.7, “Device Data Structures.”
Universal Serial Bus Interface
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