MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 301
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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By following this flow, the e300 core remains in low power state while the rest of the system is operational,
and does not get out of this state as a result of any interrupt or time-based event.
Freescale Semiconductor
2. Clear PMCCR[SLPEN] and disable the core time base unit by clearing SPCR[TBEN]. See
3. The e300 core enters low power state by accessing the HID0 register.
4. Set ACR[COREDIS] in the system arbiter register with an external master (that is, PCI). This
Section 5.3.2.4, “System Priority and Configuration Register (SPCR),”
steers all device interrupts to the PCI_INTA so the core cannot receive any interrupt requests.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Make sure that the core cannot receive any interrupt requests during the time
interval between setting HID0 and setting ACR[COREDIS]. This can be
achieved if the rest of the system is idle (during the initialization).
NOTE
for more information.
System Configuration
5-93
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