MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 554
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Sequencer
11.1.1
The I/O sequencer includes the following features:
Note that the number of CSB masters allowed to access to PCI outbound windows is restricted to no more
than four non-CPU masters or no more than two non-CPU plus the CPU. If this number is exceeded,
deadlock can occur on CSB arbitration.
11.2
The I/O sequencer has no external signals.
11.3
Table 11-1
11-2
Offset
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x78
0x80
0x88
•
•
•
Switches transactions among its ports
Contains 8 cache-line (32-byte) buffers to allow streaming of PCI transactions
Performs address translation on outbound PCI transactions
Memory Map/Register Definition
External Signal Description
POTAR0—PCI outbound translation address register 0
POBAR0—PCI outbound base address register 0
POCMR0—PCI outbound comparison mask register 0
POTAR1—PCI outbound translation address register 1
POBAR1—PCI outbound base address register 1
POCMR1—PCI outbound comparison mask register 1
POTAR2—PCI outbound translation address register 2
POBAR2—PCI outbound base address register 2
POCMR2—PCI outbound comparison mask register 2
POTAR3—PCI outbound translation address register 3
POBAR3—PCI outbound base address register 3
POCMR3—PCI outbound comparison mask register 3
POTAR4—PCI outbound translation address register 4
POBAR4—PCI outbound base address register 4
POCMR4—PCI outbound comparison mask register 4
POTAR5—PCI outbound translation address register 5
POBAR5—PCI outbound base address register 5
POCMR5—PCI outbound comparison mask register 5
shows the I/O sequencer memory map.
Features
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Register
Table 11-1. Sequencer Memory Map
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
Freescale Semiconductor
Section/Page
11.4.1/11-3
11.4.2/11-3
11.4.3/11-4
11.4.1/11-3
11.4.2/11-3
11.4.3/11-4
11.4.1/11-3
11.4.2/11-3
11.4.3/11-4
11.4.1/11-3
11.4.2/11-3
11.4.3/11-4
11.4.1/11-3
11.4.2/11-3
11.4.3/11-4
11.4.1/11-3
11.4.2/11-3
11.4.3/11-4
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