MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 341

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 7-3
Table 7-4
Freescale Semiconductor
29–30
Bits
Bits
25
26
27
28
31
0
1
2
3
4
5
6
DECAREN
Name
NOOPTI
shows how HID0[ECLK] and HID0[SBCLK] are used to configure the clk_out signal.
shows the bit definitions for HID1
PC0
PC1
PC2
PC3
PC4
PC5
PC6
FBIOB
Name
ABE
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Asserted
Negated
hreset
PLL configuration bit 0 (read-only)
PLL configuration bit 1 (read-only)
PLL configuration bit 2 (read-only)
PLL configuration bit 3 (read-only)
PLL configuration bit 4 (read-only)
PLL configuration bit 5 (read-only)
PLL configuration bit 6 (read-only)
Table 7-3. Using HID0[ECLK] and HID0[SBCLK] to Configure clk_out
0 Normal operation.
1 Decrementer loads last mtdec value for precise periodic interrupt.
Reserved, should be cleared.
Force branch indirect on the bus
0 Register indirect branch targets are fetched normally
1 Forces register indirect branch targets to be fetched externally
Address broadcast enable. Controls whether certain address-only operations (such as cache
operations) are broadcast on the bus.
0 Address-only operations affect only local caches and are not broadcast
1 Address-only operations are broadcast on the bus
Affected instructions are dcbi, dcbf, and dcbst. Note that these cache control instruction broadcasts
are not snooped by the e300 core. Refer to Section 4.3.3, “Data Cache Control,” for more information.
Reserved, should be cleared.
No-op the data cache touch instructions
0 The dcbt and dcbtst instructions are enabled
1 The dcbt and dcbtst instructions are no-oped internal to the e300 core
Decrementer auto reload
ECLK
0
0
1
1
x
Table 7-2. e300 HID0 Bit Descriptions (continued)
SBCLK
Table 7-4. HID1 Bit Descriptions
0
1
0
1
x
Bus clock (small pulse for every rising edge of sysclk)
Clock output off
Core clock/2
Core clock
Bus clock
Description
Function
clk_out
e300 Processor Core Overview
7-23