MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 672

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
Table 14-18
14-30
The following bits are described for information only. They are not under direct user control.
The following bits are controlled through the MODE0 or MODE1 fields of the descriptor header.
62–63
0–52
Bits
Bits
61
53
54
55
56
57
Reset
Field
Addr
R/W
NEW=1 Determines the configuration of the MDEU mode register (MDEUMR). This table shows the configuration
CONT
Name
Name
CICV
STIB
ALG
PD
0
—
—
describes MDEUMR fields in ‘new’ configuration.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
This bit must be programmed opposite to the CONT bit.
Message digest algorithm selection
00 SHA-160 algorithm (full name for SHA-1)
01 SHA-256 algorithm
10 MD5 algorithm
11 SHA-224 algorithm
Reserved
SSL/TLS inbound, block cipher
0 Normal operation.
1 Special operation only for SSL/TLS inbound, block cipher. Upon receiving end-of-message, the MDEU
for NEW = 1.
Reserved, must be set to zero
Continue. Most operations will require this bit to be cleared. Set only when the data to be hashed is spread
across multiple descriptors.
0 Do autopadding and complete the message digest. Used when the entire hash is performed with one
1 This hash will be continued in a subsequent descriptor. Do not autopad and do not complete the
Compare integrity check values
0 Normal operation; no ICV comparison.
1 After the message digest (ICV) is computed, compare it to the data in the MDEU’s input FIFO. If the ICVs
Figure 14-16. MDEU Mode Register (MDEUMR) in ‘New’ Configuration
performs a calculation involving the last valid byte of data written into its input FIFO (which is Pad Length)
to compute a final data size. The MDEU then processes the amount of data specified by this data size,
and completes the message digest.
descriptor, or on the last of a sequence of descriptors.
message digest.
do not match, send an error interrupt to the channel. The number of bytes to be compared is given by
the ICV size register.
—
Table 14-17. MDEUMR in ‘Old’ Configuration (continued)
Table 14-18. MDEUMR in ‘New’ Configuration
52
STIB NEW=1
53
MDEU 0x3_6000
54
R/W
0
Description
—
Description
55
CONT CICV SMAC INIT HMAC EALG
56
57
58
59
Freescale Semiconductor
60
61
62
ALG
63