MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 917
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Freescale Semiconductor
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10. (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_000x_1x10_0000]
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register. (Optional)
(Uses the PHY address (0x11) and Register address (5) placed in MIIMADD register)
Table 15-170. RGMII Mode Register Initialization Steps (continued)
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Setup MIIMADD[0000_0000_0000_0000_0001_0001_0000_0101]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize MACnADDR1/2 (Optional)
Initialize DMACTRL (Optional)
Clear MIIMCOM[Read Cycle]
Initialize GADDR n (Optional)
Initialize RBASE0–RBASE7,
Initialize TBASE0–TBASE7,
Set MIIMCOM[Read Cycle]
Initialize RCTRL (Optional)
When MIIMIND[BUSY]=0,
Initialize IMASK (Optional)
Enable Transmit Queues
Enable Receive Queues
Clear IEVENT register,
Enable Rx and Tx,
Initialize RQUEUE
Initialize TQUEUE
Enhanced Three-Speed Ethernet Controllers
15-199
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