MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 496

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Enhanced Local Bus Controller
bus. Write data becomes invalid following the falling edge of TA. LWE may, in some cases, negate high
before the end of the write access to provide additional hold time for the external memory.
Table 10-33
varied.
10-48
TRLX
Option Register Attributes
0
0
0
0
0
0
0
0
0
lists the signal timing parameters for a GPCM write access as the option register attributes are
LBCTL
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
LCLK
LALE
LCS n
LWE
LAD
XACS
TA
A
0
0
0
1
1
1
0
0
0
Notes:
t
t
t
WC
AWCS
AWE
= Write cycle time.
ACS
= Address valid to write enable time.
Address
00
10
11
00
10
11
00
10
11
= Address valid to write chip-select time.
Figure 10-35. GPCM General Write Timing Parameters
Table 10-33. GPCM Write Control Signal Timing
CSNT
0
0
0
0
0
0
1
1
1
t
AWCS
t
t
AWCS
AWE
(½)
(½)
¼
½
¼
½
0
0
1
2
0
1¾+SCY
1½+SCY
1½+SCY
1¼+SCY
(2+SCY)
(1+SCY)
Signal Timing (LCLK clock cycles)
2+SCY
2+SCY
1+SCY
1+SCY
2+SCY
t
Write Data
Latched Address
CSWP
t
t
t
WC
CSWP
WEN
t
CSWP
= Write enable negated time wrt chip-selec
= Write chip-select assertion period.
t
AWE
1
1
1
1
1
2
1
1
1
t
WEN
t
WEN
(0)
¼
0
0
0
0
0
0
0
0
1
Freescale Semiconductor
(1½+SCY)
(1½+SCY)
1¾+SCY
1¾+SCY
2+SCY
2+SCY
2+SCY
2+SCY
2+SCY
3+SCY
2+SCY
t
WC