MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 377

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Table 8-17
8.5.10
SMPRR_B, shown in
Freescale Semiconductor
12–15,
16–27
28–31
Offset 0x34
Reset 0
3–11,
Bits
0–2
W
R
0
MIXB0P
MIXA1P–
MIXA0P MIXA0 priority order. Defines which interrupt source asserts its request in the MIXA0 priority position. The
MIXA7P
Name
0
—
defines the bit fields of SMPRR_A.
System Mixed Interrupt Group B Priority Register (SMPRR_B)
2
0
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 8-13. System Mixed Interrupt Group B Priority Register (SMPRR_B)
3
0
MIXB1P
user must not program the same code to more than one priority position (0–7). These bits can be changed
dynamically. The definition of MIXA0P is as follows:
000 RTC SEC asserts its request to the MIXA0 position.
001 PIT asserts its request to the MIXA0 position.
010 PCI asserts its request to the MIXA0 position.
011 Reserved.
100 IRQ0 asserts its request to the MIXA0 position. This field for MIXA0 position is valid (must not be
101 IRQ1 asserts its request to the MIXA0 position.
110 IRQ2 asserts its request to the MIXA0 position.
111 IRQ3 asserts its request to the MIXA0 position.
Same as MIXA0P, but for MIXA1P–MIXA7P.
Write ignored, read = 0
0
ignored) if IRQ0 signal configured as an external maskable interrupt (SEMSR[SIRQ0] = 0).
Figure
1
5
0
6
MIXB2P
1
8-13, defines the priority among the sources listed in
0
8
Table 8-17. SMPRR_A Field Descriptions
0
9
MIXB3P
1
11 12
1
0
0
—
0
15 16
0
Description
1
MIXB4P
0
18 19
0
Integrated Programmable Interrupt Controller (IPIC)
1
MIXB5P
0
21 22
1
1
MIXB6P
1
24 25
0
Table
1
MIXB7P
1
Access: Read/write
8-18.
27 28
1
0
0
—
0
8-19
31
0