MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 336

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

e300 Processor Core Overview
1
7-18
28–29
Bits
All reserved bits should be set to zero for future compatibility.
18
19
20
21
22
23
24
25
26
27
29
30
31
1
Name
PMM
FE0
FE1
ME
CE
DR
FP
SE
BE
LE
IP
IR
—
RI
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Floating-point available
0 The processor prevents dispatch of floating-point instructions, including floating-point loads, stores, and
1 The processor can execute floating-point instructions and can take floating-point enabled exception type
Machine check enable
0 Machine check interrupts are disabled
1 Machine check interrupts are enabled
Floating-point exception mode 0
Single-step trace enable
0 The processor executes instructions normally
1 The processor generates a trace interrupt upon the successful completion of the next instruction
Branch trace enable
0 The processor executes branch instructions normally
1 The processor generates a trace interrupt upon the successful completion of a branch instruction
Floating-point exception mode 1
Critical interrupt enable
0 Critical interrupts disabled
1 Critical interrupts enabled; critical interrupt and rfci instruction enabled
The critical interrupt is an asynchronous implementation-specific interrupt. The critical interrupt vector offset
is 0x00A00. The rfci instruction is implemented to return from these interrupt handlers. Also, CSRR0 and
CSRR1 are used to save and restore the processor state for critical interrupts.
Interrupt prefix. The setting of this bit specifies whether an interrupt vector offset is prepended with Fs or 0s.
In the following description, nnnnn is the offset of the interrupt.
0 Interrupts are vectored to the physical address 0x000 n_nnnn
1 Interrupts are vectored to the physical address 0xFFF n_nnnn
Instruction address translation
0 Instruction address translation is disabled
1 Instruction address translation is enabled
Data address translation
0 Data address translation is disabled
1 Data address translation is enabled
Reserved. Full function. Bit 29 not reserved on e300c3 .
Performance monitor mark bit (e300c3 ). System software can set PMM when a marked process is running
to enable statistics to be gathered only during the execution of the marked process. MSR[PR] and MSR[PMM]
together define a state that the processor (supervisor or user) and the process (marked or unmarked) may
be in at any time. If this state matches an individual state specified in the PMLCa n , the state for which
monitoring is enabled, counting is enabled.
Recoverable interrupt (for system reset and machine check interrupts)
0 Interrupt is not recoverable
1 Interrupt is recoverable
Little-endian mode enable
0 The processor runs in big-endian mode
1 The processor runs in little-endian mode.
moves.
program interrupts.
Table 7-1. MSR Bit Descriptions (continued)
Description
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