MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 252
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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System Configuration
The PIT consists of a 32-bit down-counter which is decremented by a clock derived from a CSB clock or
from an external 32.768-kHz crystal. The 32-bit counter decrements to zero when loaded with a initial
value from the periodic interval timer load register (PTLDR). The periodic interval timer control register
(PTCTR) is used to enable or disable the various timer functions. The periodic interval timer event register
(PTEVR) is used to report the interrupt source. The PIT function can be disabled if needed.
Figure 5-32
5.6.2
The key features of the PIT include the following:
5.6.3
The PIT unit can operate in the following modes:
5.6.4
This section provides an overview and detailed descriptions of the PIT signals.
There is one distinct external input signal (PIT clock), defined in
5-44
PIT_CLK
•
•
•
•
•
•
•
•
Name
Maintains a 32-bit down-counter, clocked by a 32-bit prescaled input clock
32-bit PIT counter can be initialized by software to specific initial count value
Provides programmable and maskable periodic interrupt
Uses two possible clock sources: the CSB clock or an external PIT clock
PIT function can be disabled
PIT enable/disable mode
PIT periodic interrupt enable/disable mode
PIT internal/external input clock mode
PIT Features
PIT Modes of Operation
PIT External Signal Description
shows the functional PIT block diagram.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PIT_CLK
Port
Figure 5-32. Periodic Interval Timer High Level Block Diagram
Periodic interval timer.
System
Clock
Clock
PIT
Table 5-46. PIT Signal Properties
Register Interface
Periodic
Function
Interval
Timer
Table
Periodic
Interrupt
5-46.
I/O
I
Freescale Semiconductor
Reset
N/A
Pull Up
—
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