MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 267
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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5.7.5.3
Global timers reference registers, shown in
containing the 16-bit reference values for each timer’s timeout. The reference value is not reached until
GTCNRn[CNV] increments to the value in GTRFRn[TRV].
Table 5-60
5.7.5.4
Global timers capture registers (GTCPR1, GTCPR2, GTCPR3, and GTCPR4), shown in
used to latch the value of the counters according to GTMDRn[CE].
Freescale Semiconductor
13–14
Offset
Offset
0–15
Bits
Bits
15
Reset
Reset
W
W
R
R
Name
0x14(GTRFR1)
0x16(GTRFR2)
Name
0x18(GTCPR1)
0x1A(GTCPR2)
ICLK
TRV
GE
0
1
0
defines the bit fields of GTRFR.
Global Timers Reference Registers (GTRFR1–GTRFR4)
Global Timers Capture Registers (GTCPR1–GTCPR4)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Input clock source for the timer.
00 Internally cascaded input. This selection means: For ICLK1, the timer 1 input is the output of timer 2. For
01 Internal general system bus clock.
10 Internal slow go clock (divided by 16 system bus clock).
11 TIN n : corresponding TIN1, TIN2, TIN3, or TIN4 pin (falling edge).
Gate enable
0 The TGATE n signal is ignored.
1 The TGATE n signal is used to control the timer.
Timeout reference value.
16-bit timeout reference value for the corresponding timer. Set to all ones by reset.
1
ICLK2, the timer 1 input is the output of timer 2, the timer 2 input is the output of timer 3, the timer 3 input
is the output of timer 4. For ICLK3, the timer 3 input is the output of timer 4. For ICLK4 this selection means
no input clock is provided to the timer.
Figure 5-43. Global Timers Reference Registers (GTRFR1–GTRFR4)
Figure 5-44. Global Timers Capture Registers (GTCPR1–GTCPR4)
1
0x24(GTRFR3)
0x26(GTRFR4)
0x28(GTCPR3)
0x2A(GTCPR4)
1
Table 5-59. GTMDR Bit Settings (continued)
1
Table 5-60. GTRFR Bit Settings
1
Figure
1
5-43, are 16-bit memory-mapped, read/write registers
1
All zeros
Description
Description
TRV
LCV
1
1
1
1
1
System Configuration
Figure
Access: Read/Write
Access: Read only
1
5-44, are
1
5-59
15
15
1
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