MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 960

Manufacturer Part Number

MPC8313ECZQADDC

Microprocessors - MPU 8313 REV2.2 PB ENC EXT

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Interface Type

Mounting Style

Package / Case

Number Of Programmable I/os

Number Of Timers

Universal Serial Bus Interface

Offset 0x2_31A4

DPIE 1msE BSEIE BSVIE ASVIE AVVIE IDIE

DPS 1msT BSE

MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2

Reserved, should be cleared.

Data pulse interrupt enable

1-millisecond timer Interrupt enable

B session end interrupt enable

B session valid interrupt enable

A session valid interrupt enable

A VBus valid interrupt enable

USB ID interrupt enable.

Reserved, should be cleared.

Data pulse interrupt status. Set when data bus pulsing occurs on DP or DM. Data bus pulsing is only

detected when USBMODE[CM] = Host (11) and PORTSC[PP] (port power) = Off (0).

Software must write a one to clear this bit.

1-millisecond timer interrupt status. Set once every millisecond.

Software must write a one to clear this bit.

B session end interrupt status. Set when VBus has fallen below the B session end threshold.

Software must write a one to clear this bit.

Table 16-24. OTGSC Register Field Descriptions

Figure 16-21. OTG Status Control (OTGSC)

DPIS 1msS BSEIS BSVIS ASVIS AVVIS IDIS

Freescale Semiconductor

Access: Mixed