MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 116

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Memory Map
2-12
0x020–0x03
0x0_4606
0x0_4607
0x0_4610
0x07C–
0x0A4–
0x024–
0x094–
0x00C
0x01C
0x06C
0x08C
0x09C
0x0AC
0x0A0
0x0B0
0x0B4
0x0B8
0x000
0x008
0x010
0x018
0x004
0x014
0x064
0x068
0x070
0x074
0x078
0x080
0x084
0x088
0x090
Offset
8
UMSR—ULCR[DLAB] = x UART2 MODEM status register
USCR—ULCR[DLAB] = x UART2 scratch register
UDSR—ULCR[DLAB] = x UART2 DMA status register
BR0—Base register 0
BR1—Base register 1
BR2—Base register 2
BR3—Base register 3
Reserved
OR0—Options register 0
OR1—Options register 1
OR2—Options register 2
OR3—Options register 3
Reserved
MAR—UPM address register
Reserved
MAMR—UPMA mode register
MBMR—UPMB mode register
MCMR—UPMC mode register
Reserved
MRTPR—Memory refresh timer prescaler register
MDR—UPM/FCM data register
Reserved
LSOR—Special operation initiation register
Reserved
LURT—UPM refresh timer
Reserved
LTESR—Transfer error status register
LTEDR—Transfer error disable register
LTEIR—Transfer error interrupt register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Enhanced Local Bus Controller (eLBC) Registers
Register
Table 2-2. Memory Map (continued)
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
—
—
—
—
R
R
0x0000_0FF7
0x0000_ nnnn
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
0x00
0x00
0x01
—
—
—
—
—
—
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