MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 323
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Features specific to the e300 core not present on the G2 processors follow:
Freescale Semiconductor
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Integrated power management
— Internal processor/bus clock multiplier ratios
— Three power-saving modes: doze, nap, and sleep
— Automatic dynamic power reduction when internal functional units are idle
In-system testability and debugging features through JTAG boundary-scan capability
Enhancements to the register set
— The e300 core has one more HID0 bit than the G2:
Enhancements to cache implementation
— 16-Kbyte, four-way set-associative instruction and data caches on the e300c3.
— Full parity checking is performed on both instruction and data cache memory arrays
— Lockable L1 instruction and data caches—entire cache or on a per-way basis up to 3 of 4 ways
— New icbt instruction supports initialization of instruction cache
— Data cache supports four-state MESI coherency protocol (not implemented on MPC8313E)
— The instruction cache is blocked only until the critical load completes (hit under reloads
— Instruction cancel mechanism improves utilization of instruction cache by supporting
— The critical double word is simultaneously written to the cache and forwarded to the requesting
— Data cache queue sharing makes cast-outs and snoop pushes more efficient
— Provides for an optional data cache operation broadcast feature (enabled by HID0[ABE]) that
— Instruction fetch burst feature allows all instruction fetches from caching-inhibited space to be
Interrupts
— The e300 core offers hardware support for misaligned little-endian accesses. Little-endian
— The e300 core supports true little-endian mode to minimize the impact on software porting
— An input interrupt signal, cint, is provided to trigger the critical interrupt exception on the e300
Bus clock—PLL configuration signals include seven signals for settings and control: pll_cfg[0:6].
– The enable cache parity checking (ECPE) bit, HID0[1], gives the e300 core the ability to
on the e300c3
allowed)
hits-under-cancels and misses-under-cancels.
unit, thus minimizing stalls due to load delays.
allows for coherent system management. All of the data cache control instructions, except dcbz
(dcbi, dcbf, and dcbst) require that HID0[ABE] be enabled to broadcast.
performed on the bus as burst transactions
load/store accesses that are not on a word boundary, except for strings and multiples, generate
interrupts under the same circumstances as big-endian accesses.
from true little-endian systems.
core. The pm_event_in input signal can be used by the performance monitor counters to trigger
an interrupt upon overflow on the e300c3 .
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
enable the taking of a machine check interrupt based on the detection of a cache parity error
e300 Processor Core Overview
7-5
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