R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 981
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (9Mb)
Plane Priority Order: The display priority order for planes is set using DPPR; if one plane is set
in two or more places in the priority order, the place with highest priority is selected.
For example, if the setting in DPPR is H'00CBD888, then the results of the priority order and
display on/off settings are as follows.
19.4.11 Blinking
For each plane, blinking operation can be performed by using the display area start address 0 and
1 registers.
Usually, double buffer control is performed for each plane according to the setting of the PnBM
bit in PnMR. However, blinking is performed with the period specified by the PnBTA and PnBTB
bits in PnBTR by setting the PnBM bits in PnMR to 10 (Auto display change mode (blinking
mode)). If the PnBTA and PnBTB bits are set to 0, operation is the same as when set to 1.
Plane with priority 1
Plane with priority 2
Plane with priority 3
Plane with priority 4
Plane with priority 5
Plane with priority 6
Display off planes
Operation of
the display unit (DU)
Blinking period
setting
(Internal counter)
VSYNC
BTA-1
PnBTA (A0 display period is set)
PnBTB (A1 display period is set)
(m-1)th frame
A0 is displayed on screen
BTA
m-th frame
Plane 1
No corresponding plane
No corresponding plane
Plane 6
Plane 4
Plane 5
Plane 2 and plane 3
Buffer switching performed
according to blinking period
0
Rev.1.00 Jan. 10, 2008 Page 949 of 1658
First frame
A1 is displayed on screen
A0: Display area start address 0
A1: Display area start address 1
19. Display Unit (DU)
1
REJ09B0261-0100
Second frame
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