R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 315

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(4)
INTREQ is a 32-bit readable and conditionally writable register that indicates which of the IRQ
[n] (n = 0 to 7) interrupts is currently asserting a request for the INTC.
Even if an interrupt is masked by the setting in INTPRI or INTMSK0, operation of the
corresponding INTREQ bit is not affected.
Notes: 1. n = 0 to 7
Initial value:
Initial value:
Bit
31
30
29
28
27
26
25
24
23 to 0 ⎯
R/W:
R/W:
Interrupt Source Register (INTREQ)
Bit:
Bit:
2. Write 1 to the bit if it should not be cleared yet.
3. For the method of clearing the IRQ interrupt request that has been detected by level
Name
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
R/(W) R/(W)
sensing, refer to section 10.7.3, Clearing IRQ and IRL Interrupt Requests.
IR0
31
15
⎯
R
0
0
Initial
Value
0
0
0
0
0
0
0
0
All 0
IR1
30
14
⎯
R
0
0
R/(W)
IR2
29
13
⎯
R
0
0
R/W
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R
R/(W)
IR3
28
12
⎯
R
0
0
R/(W)
IR4
27
11
⎯
R
Edge Detection
(IRQnS = 00 or 01)
[When read]
0: The corresponding IRQ
1: The corresponding IRQ
[When written]
Reserved
These bits are always read as 0. The write value should always
be 0.
0
0
When clearing each bit, write a
0 after having read a 1 from it.
Writing 1 to the bit is ignored.
interrupt request has not
been detected.
interrupt request has been
detected.
R/(W)
IR5
26
10
⎯
R
0
0
R/(W)
IR6
25
⎯
R
0
9
0
*
R/(W)
2
IR7
24
⎯
R
0
8
0
*
1
23
⎯
⎯
R
R
0
7
0
Description
Rev.1.00 Jan. 10, 2008 Page 283 of 1658
22
⎯
⎯
R
R
0
6
0
Level Detection
(IRQnS = 10 or 11)
[When read]
(ICR0.LVLMODE = 0)
0: The corresponding interrupt
1: The corresponding interrupt
[When read]
(ICR0.LVLMODE = 1)
0: The corresponding IRQ
1: The corresponding IRQ
Writing have no effect.
21
⎯
⎯
R
R
0
5
0
source has not been
detected.
source has been detected.
interrupt pin is not asserted.
interrupt pin is asserted, but
the CPU has not accepted
the interrupt request yet.
10. Interrupt Controller (INTC)
20
⎯
⎯
R
R
0
4
0
19
⎯
⎯
R
R
0
3
0
REJ09B0261-0100
18
⎯
⎯
R
R
0
2
0
*
1
17
⎯
⎯
*
R
R
0
1
0
3
16
⎯
⎯
R
R
0
0
0