R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 953

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19.3.52 External Synchronization Control Register (ESCR)
The external synchronization control register (ESCR) controls the dot clock.
Internal update:
Internal update:
Bit
31 to 21 ⎯
20
19 to 17 ⎯
16
15 to 5
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
DCLKSEL
DCLKDIS 0
31
15
R
R
0
0
30
14
R
R
0
0
Initial
Value
All 0
0
All 0
All 0
29
13
R
R
0
0
28
12
R
R
0
0
R/W
R
R/W
R
R/W
R
27
11
R
R
0
0
Internal
Update Description
None
None
26
10
R
R
0
0
25
R
R
0
9
0
Reserved
These bits are always read as 0. The write value
should always be 0.
DOTCLKIN Select
To enable this bit, the DCKE bit in DEFR should
be set to 1. In the initial state, this bit is fixed to 0.
0: The input dot clock source is the DCLKIN pin
1: The input dot clock is DUck
Reserved
These bits are always read as 0. The write value
should always be 0.
DOTCLKOUT Disable
0: DOTCLKOUT is output.
1: DOTCLKOUT is not output.
Reserved
These bits are always read as 0. The write value
should always be 0.
24
This setting should be made such that the
frequency of the frequency-divided dot clock
generated by the dot clock generation circuit is
50 MHz or lower.
DOTCLKOUT is fixed to low level.
R
R
0
8
0
23
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 921 of 1658
22
R
R
0
6
0
21
R
R
0
5
0
DCLK
R/W
R/W
SEL
20
0
4
0
R/W
19. Display Unit (DU)
19
R
0
3
0
REJ09B0261-0100
FRQSEL
R/W
18
R
0
2
0
R/W
17
R
0
1
0
DCLK
R/W
R/W
DIS
16
0
0
0

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