R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 70

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

2. Programming Model
Table 2.2
(5)
Information is transferred between the FPU and CPU via FPUL.
Rev.1.00 Jan. 10, 2008 Page 38 of 1658
REJ09B0261-0100
Field Name
Cause
Enable
Flag
Floating-Point Communication Register (FPUL) (32 bits, Initial Value = Undefined)
<Big endian>
<Little endian>
Floating-point register
Floating-point register
FPU exception
cause field
FPU exception
enable field
FPU exception flag
field
Bit Allocation for FPU Exception Handling
Memory area
Memory area
Figure 2.5 Relationship between SZ bit and Endian
Notes: 1. In the case of SZ = 0 and PR = 0, DR register can not be used.
8n
4n+3
63
63
63
63
63
63
2. The bit-location of DR register is used for double precision format when PR = 1.
FR (2i)
FR (2i)
FPU
Error (E)
Bit 17
None
None
(In the case of (2), it is used when PR is changed from 0 to 1.)
8n+3
(1) SZ = 0
DR (2i)
32 31
DR (2i)
4n
32 31
4m+3
8n+4
FR (2i+1)
FR (2i+1)
Invalid
Operation (V)
Bit 16
Bit 11
Bit 6
8n+7
*
1,
4m
*
0
0
0
0
0
0
2
8n+3
63
63
63
FR (2i)
(2) SZ = 1, PR = 0
Division
by Zero (Z)
Bit 15
Bit 10
Bit 5
DR (2i)
8n
32 31
8n+7
FR (2i+1)
8n+4
*
0
0
2
0
Overflow
(O)
Bit 14
Bit 9
Bit 4
8n+7
63
63
63
FR (2i)
(3) SZ = 1, PR = 1
8n+4
Underflow
(U)
Bit 13
Bit 8
Bit 3
DR (2i)
32 31
8n+3
FR (2i+1)
8n
0
0
Inexact
(I)
Bit 12
Bit 7
Bit 2
0