R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 781

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

15.6
To change the frequency of the internal clock and the local bus clock (CLKOUT) with software,
set frequency control registers FRQCR0 and FRQCR1 according to the following procedure.
Tables 15.8 to 15.11 list the selectable combinations of frequencies.
15.6.1
When changing the frequency of a clock except the bus clock, disable counting-up by the WDT.
The following describes the procedure for changing the frequency.
1. In FRQCR1, set a value (other than H'0) in the bit corresponding to the clock for which you
2. Set H'CF000001 in FRQCR0 to enable execution of the sequence that changes the frequency.
3. When H'00000000 is read from FRQCR0, the sequence that changes the frequency has
Note: * When setting a value except H'0 in the MFC3 to MFC0 bits in FRQCR1 to change the
15.6.2
When changing the bus clock frequency, start counting-up by the WDT after the oscillation of
PLL circuit 2 is stable. When a WDT overflow occurs during counting, this LSI resumes
operation.
Figures 15.2 and 15.3 show the timing of the CLKOUT and CLKOUTENB pins when the bus
clock frequency is changed.
The following describes the procedure for changing the frequency.
1. Write 0 to the TME bit in WDTCSR to stop the WDT.
2. In WDTBST, after the oscillation of PLL circuit 2 is stable, set the time that can elapse before
3. In FRQCR1, set a value (except H'0) in the bit corresponding to the clock for which you want
want to change the division ratio.*
The sequence that changes the frequency starts.
finished. The internal clock has been changed to the clock with the specified division ratio.
the LSI resumes operation. Writing H'55000001 sets the minimum value. Writing H'55000000
sets the maximum value.
to change the division ratio.*
How to Change the Frequency
Changing the Frequency of Clocks Other than the Bus Clock
Changing the Bus Clock Frequency
DDR clock frequency, switch SDRAM to the self-refreshing state before executing
step (2) above. For details on how to switch to or release the self-refreshing state, see
section 12, DDR2-SDRAM Interface (DBSC2).
Rev.1.00 Jan. 10, 2008 Page 749 of 1658
15. Clock Pulse Generator (CPG)
REJ09B0261-0100