R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1108

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21. Serial Communication Interface with FIFO (SCIF)
(2)
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCIF_SCK pin can be selected as the SCIF's serial clock, according to the settings of the C/A
bit in SCSMR and the CKE1 and CKE0 bits in SCSCR. For details on SCIF clock source
selection, see table 21.5.
When an external clock is input to the SCIF_SCK pin, the clock frequency should be 16 times the
bit rate used.
When the SCIF is operated on an internal clock, a clock with frequency of 16 times the bit rate is
output from the SCIF_SCK pin.
(3)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0,
then initialize the SCIF as described below.
When the operating mode or transfer format, etc., is changed, the TE and RE bits must be cleared
to 0 before making the change using the following procedure.
1. When the TE bit is cleared to 0, SCTSR is initialized. Note that clearing the TE and RE bits to
2. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND flag in
3. When an external clock is used, the clock should not be stopped during operation, including
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0 does not change the contents of SCFSR, SCFTDR, or SCFRDR.
SCFSR has been set. The TE bit can also be cleared to 0 during transmission, but the data
being transmitted goes to the mark state after the clearance. Before setting TE again to start
transmission, the TFRST bit in SCFCR should first be set to 1 to reset SCFTDR.
initialization, since operation will be unreliable in this case.
Clock
SCIF Initialization (Asynchronous Mode)