R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 356

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
10.4
There are four types of interrupt sources, NMI, IRQ, IRL, and on-chip module interrupts. Each
interrupt has a priority level (16 to 0). Level 16 is the highest and level 1 is the lowest. When the
level is set to 0, the interrupt is masked and interrupt requests are ignored.
10.4.1
The NMI interrupt has the highest priority of level 16. The interrupt is always accepted unless the
BL bit in SR of the CPU is set to 1. In sleep mode, the interrupt is accepted even if the BL bit is
set to 1.
According to a setting, the NMI interrupt can be accepted even if the BL bit is set to 1.
Input from the NMI pin is detected at the edge. The NMI edge select bit (NMIE) in ICR0 is used
to select from the rising or falling edge. After the NMIE bit in ICR0 is modified, the NMI
interrupt is not detected for up to six bus clock cycles.
When the INTMU bit in the CPUOPM is set to 1, the interrupt mask level (IMASK) in SR is
automatically set to level 15. When the INTMU bit in CPUOPM is cleared to 0, the IMASK value
in SR is not affected by accepting an NMI interrupt.
10.4.2
(1)
The IRQ interrupt is valid when 1 is written to the IRLM0 and IRLM1 bits in ICR0 and pins
IRQ/IRL7 to IRQ/IRL0 are used for independent interrupts. The rising edge, falling edge, low
level, and high level detections are enabled by setting the IRQnS1 and IRQnS0 bits (n = 0 to 7).
The priority of interrupts is set by INTPR1.
If an IRQ interrupt request is detected by the low level or high level detection, the pin state of IRQ
interrupt state should be retained until interrupt handling starts after interrupts are accepted.
When the INTMU bit in CPUOPM is set to 1, the interrupt mask level (IMASK) in SR is
automatically set to the level of the accepted interrupt. When the INTMU bit in CPUOPM is set to
0, the IMASK value in SR is not affected by accepting an IRQ interrupt.
Rev.1.00 Jan. 10, 2008 Page 324 of 1658
REJ09B0261-0100
Independence from ICR0.LVLMODE Setting
Interrupt Sources
NMI Interrupts
IRQ Interrupts