R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 191

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.2.6
Bit
7
6 to 3
2
1
0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Page Table Entry Assistance Register (PTEA)
Bit Name
ME
TI
AT
31
15
R
R
0
0
30
14
R
R
0
0
R/W
29
13
R
0
Initial
Value
0
All 0
0
0
0
R/W
28
12
R
0
R/W
27
11
R
0
R/W
R/W
R
R/W
R
R/W
EPR
R/W
26
10
R
0
Description
TLB Extended Mode Switching
0: TLB compatible mode
1: TLB extended mode
For modifying the ME bit value, always set the TI bit to
1 to invalidate the contents of ITLB and UTLB. The
selection of TLB operating mode made by the ME bit
does not affect the functionality or operation of the
PMB.
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
TLB Invalidate Bit
Writing 1 to this bit invalidates (clears to 0) all valid
UTLB/ITLB bits. This bit is always read as 0.
Reserved
For details on reading from or writing to this bit, see
description in General Precautions on Handling of
Product.
Address Translation Enable Bit
These bits enable or disable the MMU.
0: MMU disabled
1: MMU enabled
MMU exceptions are not generated when the AT bit is
0. In the case of software that does not use the MMU,
the AT bit should be cleared to 0.
R/W
25
R
0
9
R/W
24
R
0
8
R/W
23
R
0
7
R/W
Rev.1.00 Jan. 10, 2008 Page 159 of 1658
22
R
0
6
ESZ
7. Memory Management Unit (MMU)
R/W
21
R
0
5
R/W
20
R
0
4
19
R
R
0
3
0
REJ09B0261-0100
18
R
R
0
2
0
17
R
R
0
1
0
16
R
R
0
0
0

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