R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1237

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24.3.15 Data Timeout Register (DTOUTR)
DTOUTR specifies the period to generate a data timeout. The 16-bit counter (DTOUTC) and a
prescaler, to which the peripheral bus does not have access, count the peripheral clock to monitor
the data timeout. The prescaler always counts the peripheral clock, and outputs a count pulse for
every 10,000 peripheral clock cycles. The initial value of DTOUTC is 0, and DTOUTC starts
counting the prescaler output from the start of the command sequence. DTOUTC is cleared when
the command sequence has ended, or when the command sequence has been aborted by setting the
CMDOFF bit to 1, after which the DTOUTC stops counting the prescaler output.
When the command sequence does not end, DTOUTC continues counting the prescaler output,
and enters the data timeout error states when the number of prescaler outputs reaches the number
specified in DTOUTR. When the DTERIE bit in INTCR1 is set to 1, the DTERI flag in INTSTR1
is set. As DTOUTC continues counting prescaler output, the DTERI flag setting condition is
repeatedly generated. To perform data timeout error handling, the command sequence should be
aborted by setting the CMDOFF bit to 1, and then the DTERI flag should be cleared to prevent
extra-interrupt generation.
For a command with data busy status, data timeout cannot be monitored since the command
sequence is terminated before entering the data busy state. Timeout in the data busy state should
be monitored by firmware.
Initial value:
Bit
15 to 0
R/W:
Bit:
Bit Name
DTOUTR
R/W
15
1
R/W
14
1
R/W
13
1
Initial
Value
All 1
R/W
12
1
R/W
11
R/W
R/W
1
R/W
10
1
Description
Data Timeout Time/10,000
Data timeout time: Peripheral clock cycle × DTOUTR
setting value × 10,000.
R/W
9
1
R/W
8
1
DTOUTR
R/W
7
1
Rev.1.00 Jan. 10, 2008 Page 1205 of 1658
R/W
6
1
24. Multimedia Card Interface (MMCIF)
R/W
5
1
R/W
4
1
R/W R/W
3
1
REJ09B0261-0100
2
1
R/W
1
1
R/W
0
1