R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 194

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7. Memory Management Unit (MMU)
7.2.8
When the specific resource is changed, IRMCR controls whether the instruction fetch is
performed again for the next instruction. The specific resource means the part of control registers,
TLB, and cache.
In the initial state, the instruction fetch is performed again for the next instruction after changing
the resource. However, the CPU processing performance will be lowered because the instruction
fetch is performed again for the next instruction every time the resource is changed. Therefore, it
is recommended that each bit in IRMCR is set to 1 and the specific instruction should be executed
after all necessary resources have been changed prior to execution of the program which uses
changed resources.
For details on the specific sequence, see descriptions in each resource.
Rev.1.00 Jan. 10, 2008 Page 162 of 1658
REJ09B0261-0100
Bit
31 to 5
4
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Instruction Re-Fetch Inhibit Control Register (IRMCR)
Bit Name
⎯
R2
31
15
R
R
0
0
30
14
R
R
0
0
Initial
Value
All 0
0
29
13
R
R
0
0
28
12
R
R
0
0
27
11
R/W
R
R/W
R
R
0
0
26
10
R
R
0
0
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Re-Fetch Inhibit 2 after Register Change
When MMUCR, PASCR, CCR, PTEH, or RAMCR is
changed, this bit controls whether re-fetch is performed
for the next instruction.
0: Re-fetch is performed
1: Re-fetch is not performed
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
22
R
R
0
6
0
21
R
R
0
5
0
R/W R/W R/W R/W R/W
R2
20
R
0
4
0
R1
19
R
0
3
0
18
LT
R
0
2
0
MT
17
R
0
1
0
MC
16
R
0
0
0