R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1145

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
12
11
10
Bit Name
TDREQ
⎯
RCRDY
Initial
Value
0
0
0
R/W
R
R
R
Description
Transmit Data Transfer Request
0: Indicates that the size of empty space in the transmit
1: Indicates that the size of empty space in the transmit
A transmit data transfer request is issued when the
empty space in the transmit FIFO exceeds the size
specified by the TFWM bit in SIFCTR.
When using transmit data transfer through the DMAC,
this bit is always cleared by one DMAC access. After
DMAC access, when conditions for setting this bit are
satisfied, the SIOF again indicates 1 for this bit.
•
•
•
Reserved
This bit is always read as 0. The write value should
always be 0.
Receive Control Data Ready
0: Indicates that SIRCR stores no valid data
1: Indicates that SIRCR stores valid data
•
•
•
•
FIFO does not exceed the size specified by the
TFWM bit in SIFCTR.
FIFO exceeds the size specified by the TFWM bit in
SIFCTR.
This bit is valid when the TXE bit in SICTR is 1.
This bit indicates a state; if the size of empty space
in the transmit FIFO is less than the size specified
by the TFWM bit in SIFCTR, this bit is automatically
cleared to 0.
To enable the issuance of this interrupt source, set
the TDREQE bit in SIIER to 1.
If SIRCR is written to when this bit is set to 1,
SIRCR is overwritten to by the latest data.
This bit is valid when the RXE bit in SICTR is set to
1.
This bit indicates the state of the SIOF. If SIRCR is
read from, this bit is automatically cleared to 0.
To enable the issuance of this interrupt source, set
the RCRDYE bit in SIIER to 1.
Rev.1.00 Jan. 10, 2008 Page 1113 of 1658
22. Serial I/O with FIFO (SIOF)
REJ09B0261-0100