R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 384

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 352 of 1658
REJ09B0261-0100
Pin Name
BACK
CE2A*
CE2B*
MODE5,
MODE6,
MODE7
MODE8
MODE9
1
2
,
Function
Bus Request
Acknowledge
PCMCIA Card
Select
Bus Width and
Memory Type
for Area 0
Endian
Switching
Master/Slave
Switching
I/O
O
O
I
I
I
Description
Bus request acknowledge signal
Multiplexed with Port M0 (GPIO input/output).
CE2A , CE2B in PCMCIA interface setting
Only valid in little endian mode
CE2A: Multiplexed with DACK2 (DMAC output),
CE2B: Multiplexed with MODE12, DACK3
Signals for setting area 0 bus width (MODE5,
MODE6) and MPX interface (MODE7: high level
selects SRAM and low level selects MPX) at a
power-on reset by the PRESET pin
MODE5: Multiplexed with SIOF_MCLK (SIOF
MODE6: Multiplexed with SIOF_SYNC (SIOF
MODE7: Multiplexed with SCIF3_RXD (SCIF
Signal for setting endian at a power-on reset by
the PRESET pin
Multiplexed with SCIF3_SCK (SCIF
Signal indicating master/slave at a power-on
reset by the PRESET pin
Multiplexed with SCIF4_TXD (SCIF output), FD1
(FLCTL input/output) and Port N2 (GPIO output).
input/output), FD0 (FLCTL input/output) and Port
N3 (GPIO output)
Port L5 (GPIO input/output)
(DMAC output) and Port L0 (GPIO
input/output)
input)
input/output)
input) and FALE (FLCTL output)