R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 355
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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When a GPIO port pin is used as an interrupt pin, the GPIO notifies the INTC of the interrupt
when the GPIO detects an interrupt. The INTC indicates the interrupt as a 1-bit source in INT2A0
or INT2A1. In this case, the port and the pin number which interrupts are generated from can be
identified by referring to INT2B6. Also, the ports can be specified by referring to the INTEVT
code.
Bit
18
17
16
15 to
11
10
9
8
7 to
3
2
1
0
Name
PORTH3E 0
PORTH2E 0
PORTH1E 0
⎯
PORTE5E 0
PORTE4E 0
PORTE3E 0
⎯
PORTE2E 0
PORTE1E 0
PORTE0E 0
Initial
Value R/W
All 0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Enables interrupt request from pin 3
of port H.
Enables interrupt request from pin 2
of port H.
Enables interrupt request from pin 1
of port H.
Reserved
These bits are always read as 0.
The write value should always be 0.
Enables interrupt request from pin 5
of port E.
Enables interrupt request from pin 4
of port E.
Enables interrupt request from pin 3
of port E.
Reserved
These bits are always read as 0.
The write value should always be 0.
Enables interrupt request from pin 2
of port E.
Enables interrupt request from pin 1
of port E.
Enables interrupt request from pin 0
of port E.
Rev.1.00 Jan. 10, 2008 Page 323 of 1658
10. Interrupt Controller (INTC)
Description
Enables a GPIO interrupt
request for each pin.
0: Disable the
1: Enable the
corresponding interrupt
request
corresponding interrupt
request
REJ09B0261-0100
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