R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 908

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19. Display Unit (DU)
19.3.21 DE Signal Start Register (DESR)
The DE signal start register (DESR) sets the rising edge position of the DE signal. The value is
retained during power-on reset and manual reset.
Internal update:
Internal update:
Rev.1.00 Jan. 10, 2008 Page 876 of 1658
REJ09B0261-0100
Bit
31 to 11 ⎯
10 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
DES
31
15
—
—
R
R
0
0
30
—
14
—
R
R
0
0
Initial
Value
All 0
Undefined R/W
29
13
—
—
R
R
0
0
28
12
—
—
R
R
0
0
R/W
R
27
11
—
—
R
R
0
0
Internal
Update
⎯
Yes
R/W
26
10
—
—
O
R
0
R/W
25
—
—
R
O
0
9
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
DE Signal Start
The DE signal rising edge position should be set
in dot clock units relative to the falling edge of
the HSYNC signal.
The DE signal rises (setting + 1) cycles after the
falling edge of the HSYNC signal. Hence the DE
signal cannot be made to rise in the same cycle
as the falling edge of the HSYNC signal.
During the vertical blanking interval the level is
fixed at low level.
R/W
24
—
—
R
O
0
8
R/W
23
—
—
R
O
0
7
R/W
22
—
—
O
R
0
6
R/W
DES
21
—
—
O
R
0
5
R/W
20
—
—
R
O
0
4
R/W
19
—
—
R
O
0
3
R/W
18
—
—
R
O
0
2
R/W
17
—
—
O
R
0
1
R/W
16
—
—
O
R
0
0