R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1165

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
22.4.4
(1)
Writing and reading of transmit/receive data is performed for the following registers.
• Transmit data writing: SITDR (32-bit access)
• Receive data reading: SIRDR (32-bit access)
Figure 22.5 shows the transmit/receive data and the SITDR and SIRDR bit alignment.
Note: In the figure, only the shaded areas are transmitted or received as valid data. Therefore,
Monaural or stereo can be specified for transmit data by the TDLE bit and TDRE bit in SITDAR.
Monaural or stereo can be specified for receive data by the RDLE bit and RDRE bit in SIRDAR.
To achieve left and right same audio output while stereo is specified for transmit data, set the
TLREP bit in SITDAR. Tables 22.8 and 22.9 show the audio mode specification for transmit data
and that for receive data, respectively.
Transmit/Receive Data
access must be made in byte units for 8-bit data, and in word units for 16-bit data. Data in
not shaded areas is not transmitted or received.
Register Allocation of Transfer Data
(a) 16-bit stereo data
(b) 16-bit monaural data
(c) 8-bit monaural data
(d) 16-bit stereo data (left and right same audio output)
Figure 22.5 Transmit/Receive Data Bit Alignment
31
31
31
31
Data
L-channel data
24 23
24 23
24 23
24 23
Data
Data
16 15
16 15
16 15
16 15
Rev.1.00 Jan. 10, 2008 Page 1133 of 1658
R-channel data
8 7
8 7
8 7
8 7
22. Serial I/O with FIFO (SIOF)
0
0
0
0
REJ09B0261-0100

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