R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 232

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7. Memory Management Unit (MMU)
7.8.2
This LSI enters 29-bit address mode after a power-on reset. Transition is made to 32-bit address
extended mode by setting the SE bit in PASCR to 1. In 32-bit address extended mode, the MMU
operates as follows.
1. When the AT bit in MMUCR is 0, virtual addresses in the U0, P0, or P3 area become 32-bit
2. When the AT bit in MMUCR is 1, virtual addresses in the U0, P0, or P3 area are translated to
3. Regardless of the setting of the AT bit in MMUCR, bits 31 to 29 in physical addresses become
7.8.3
In 32-bit address extended mode, virtual addresses in the P1 or P2 area are translated according to
the PMB mapping information. The PMB has 16 entries and configuration of each entry is as
follows.
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physical addresses. Addresses in the P1 or P2 area are translated according to the PMB
mapping information. B'10 should be set to the upper 2 bits of virtual page number
(VPN[31:30]) in the PMB in order to indicate P1 or P2 area. The operation is not guaranteed
when the value except B'10 is set to these bits.
32-bit physical addresses according to the TLB conversion information. Addresses in the P1 or
P2 area are translated according to the PMB mapping information. B'10 should be set to the
upper 2 bits of virtual page number (VPN[31:30]) in the PMB in order to indicate P1 or P2
area. The operation is not guaranteed when the value except B'10 is set to these bits.
B'111 in the control register area (addresses H'FC00 0000 to H'FFFF FFFF). When the control
register area is recorded in the UTLB and accessed, B'111 should be set to PPN[31:29].
Transition to 32-Bit Address Extended Mode
Privileged Space Mapping Buffer (PMB) Configuration
Entry 0
Entry 1
Entry 2
Entry 15
VPN[31:24]
VPN[31:24]
VPN[31:24]
VPN[31:24]
Figure 7.27 PMB Configuration
V
V
V
V
PPN[31:24]
PPN[31:24]
PPN[31:24]
PPN[31:24]
SZ[1:0]
SZ[1:0]
SZ[1:0]
SZ[1:0]
C
C
C
C UB
UB
UB
UB
WT
WT
WT
WT