R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 407

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
9, 8
7
Bit Name
SZ
RDSPL
Initial
Value
11
1
R/W
R/W*
R/W
Description
Bus Width
In CS0BCR, the external pins (MODE5 and MODE6) to
specify the bus size are sampled at a power-on reset.
When using the MPX interface, set these bits to 00 or
11. When using the byte control SRAM interface, set
these bits to 00, 10 or 11.
00: 64 bits (can be specified when the MODE 12 and
01: 8 bits
10: 16 bits
11: 32 bits
Note: * The SZ bits in CS0BCR are read-only. When
RD Hold Cycle
Specifies the number of cycles to be inserted in the
hold time for the read data sample timing of RD. When
setting this bit to 1, specify the number of RD negation-
CSn negation delay cycles set by the RDH bit in
CSnWCR as 1 or more. Also the RD negation-CSn
negation delay cycle is reduced 1 cycle when this bit is
set to 1 (valid only when the SRAM interface, burst
ROM interface, or byte control SRAM interface is
selected).
0: No hold cycle inserted
1: 1 hold cycle inserted
MODE 11 pins are set to 1 and 0 respectively.)
area 0 is set to the MPX interface by the
MODE7 pin, the SZ bits in CS0BCR should be
set to 00 or 11.
Rev.1.00 Jan. 10, 2008 Page 375 of 1658
11. Local Bus State Controller (LBSC)
REJ09B0261-0100