R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 78

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3. Instruction Set
Table 3.1
A slot illegal instruction exception may occur when a specific instruction is executed in a delay
slot. For details, see section 5, Exception Handling. The instruction following BF/S or BT/S for
which the branch is not taken is also a delay slot instruction.
(5)
The T bit in SR is used to show the result of a compare operation, and is referenced by a
conditional branch instruction. An example of the use of a conditional branch instruction is shown
below.
ADD
CMP/EQ R1, R0
BT
In an RTE delay slot, the SR bits are referenced as follows. In instruction access, the MD bit is
used before modification, and in data access, the MD bit is accessed after modification. The other
bits—S, T, M, Q, FD, BL, and RB—after modification are used for delay slot instruction
execution. The STC and STC.L SR instructions access all SR bits after modification.
(6)
An 8-bit constant value can be specified by the instruction code and an immediate value. 16-bit
and 32-bit constant values can be defined as literal constant values in memory, and can be
referenced by a PC-relative load instruction.
MOV.W @(disp, PC), Rn
MOV.L
There are no PC-relative load instructions for floating-point operations. However, it is possible to
set 0.0 or 1.0 by using the FLDI0 or FLDI1 instruction on a single-precision floating-point
register.
Rev.1.00 Jan. 10, 2008 Page 46 of 1658
REJ09B0261-0100
TARGET
T Bit
Constant Values
#1, R0
TARGET ; Branches to TARGET if T bit = 1 (R0 = R1)
@(disp, PC), Rn
Execution Order of Delayed Branch Instructions
BRA
ADD
:
:
target-inst
; T bit is not changed by ADD operation
; If R0 = R1, T bit is set to 1
TARGET
Instructions
(Delayed branch instruction)
(Delay slot)
(Branch destination instruction)
BRA
↓
ADD
↓
target-inst
Execution Order