R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 725

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
14.3.9
DMARS are 16-bit readable/writable registers. DMARS0, DMARS1, DMARS2, DMARS3,
DMARS4, and DMARS5 specify DMA transfer request source from peripheral modules for
channels 0 and 1, channels 2 and 3, channels 4 and 5, channels 6 and 7, channels 8 and 9, and
channels 10 and 11 respectively. These registers can specify the transfer request of SCIF0 to
SCIF5, HAC0, HAC1, HSPI, SIOF, SSI0, SSI1, FLCTL, and MMCIF.
When MID/RID other than the values listed in table 14.3 is specified, the operation of this LSI is
not guaranteed. The transfer request from DMARS is valid only when the resource select bits RS3
to RS0 have been set to B'1000 for CHCR. When the bits are not set to B'1000, transfer request
source is not accepted even if DMARS has been specified.
• DMARS0
• DMARS1
• DMARS2
• DMARS3
Initial value:
Initial value:
Initial value:
Initial value:
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
DMA Extended Resource Selectors 0 to 5 (DMARS0 to DMARS5)
R/W
R/W
R/W
R/W
15
15
15
15
0
0
0
0
R/W
R/W
R/W
R/W
14
14
14
14
0
0
0
0
R/W
R/W
R/W
R/W
13
13
13
13
Ch1MID
0
Ch3MID
0
Ch5MID
0
Ch7MID
0
R/W
R/W
R/W
R/W
12
12
12
12
0
0
0
0
R/W
R/W
R/W
R/W
11
11
11
11
0
0
0
0
R/W
R/W
R/W
R/W
10
10
10
10
0
0
0
0
R/W
R/W
R/W
R/W
9
0
9
0
9
0
9
0
Ch1RID
Ch3RID
Ch5RID
Ch7RID
R/W
R/W
R/W
R/W
8
0
8
0
8
0
8
0
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
14. Direct Memory Access Controller (DMAC)
R/W
R/W
R/W
R/W
Rev.1.00 Jan. 10, 2008 Page 693 of 1658
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
Ch0MID
Ch2MID
Ch4MID
Ch6MID
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
REJ09B0261-0100
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
Ch0RID
Ch2RID
Ch4RID
Ch6RID
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0

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