R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 441

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

When software wait insertion is specified by CSnWCR, the external wait input signal, RDY, is
also sampled. The RDY signal sampling timing is shown in figure 11.10, where a single wait cycle
is specified as a software wait. The RDY signal is sampled at the transition from the Tw state to
the T2 state. Therefore, the assertion of the RDY signal has no effect in the T1 cycle or in the first
Tw cycle. The RDY signal is sampled on the rising edge of the clock.
(Wait Cycle Insertion by RDY Signal, RDY Signal Is Synchronous Input)
In this example, DACKn is active-high. (The circles indicate the sampling timing.)
CLKOUT
A25 to A0
CSn
R/W
RD
(In reading)
D31 to D0
(In reading)
WEn
(In writing)
D31 to D0
(In writing)
BS
RDY
DACKn
: Sampling Timing
Figure 11.10 SRAM Interface Wait Timing
T1
Tw
Twe
Rev.1.00 Jan. 10, 2008 Page 409 of 1658
11. Local Bus State Controller (LBSC)
T2
REJ09B0261-0100