R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 310
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 310 of 1694
- Download datasheet (9Mb)
10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 278 of 1658
REJ09B0261-0100
Bit
25
24
23
22
Name
NMIB
NMIE
IRLM0
IRLM1
*
*
1
1
*
*
2
2
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
NMI Block Mode
Selects whether an NMI interrupt is held until the BL bit
in SR is cleared to 0 or detected immediately when the
BL bit in SR of the CPU is set to 1.
0: An NMI interrupt is held when the BL bit in SR is set
1: An NMI interrupt is not held when the BL bit in SR is
Note: If interrupts are accepted with the BL bit in SR
NMI Edge Select
Selects whether an interrupt request signal to the NMI
pin is detected at the rising edge or the falling edge.
0: An interrupt request is detected at the falling edge of
1: An interrupt request is detected at the rising edge of
IRL Pin Mode 0
Selects whether IRQ/IRL3 to IRQ/IRL0 are used as
encoded interrupt requests (IRL3 to IRL0) or as four
independent interrupts (IRQ3 to IRQ0 interrupts).
0: IRQ/IRL3 to IRQ/IRL0 are used as the encoded
1: IRQ/IRL3 to IRQ/IRL0 are used as four independent
IRL Pin Mode 1
Selects whether IRQ/IRL7 to IRQ/IRL4 are used as 4-
bit level-encoded interrupt requests (IRL7 to IRL4
interrupts) or as four independent interrupts (IRQ7 to
IRQ4 interrupts).
0: IRQ/IRL7 to IRQ/IRL4 are used as the 4-bit level-
1: IRQ/IRL7 to IRQ/IRL4 are used as four independent
interrupt requests (initial value)
interrupt requests
encoded interrupt requests (initial value)
interrupt requests
to 1 (initial value)
set to 1
NMI input (initial value)
NMI input
set to 1, information saved for any previous
exception (SSR, SPC, SGR, and INTEVT) is lost.
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