R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 377

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.7.3
To clear the interrupt request retained in the INTC, follow the procedure below.
(1)
(2)
(a)
(b) ICR0.LVLMODE = 1
The INTC does not retain the interrupt source even if IRQ interrupts are detected at level detection
or IRL interrupt requests are detected.
Clearing Interrupt Request Independent from ICR0.LVLMODE Setting
Clearing Interrupt Request Dependent on ICR0.LVLMODE Setting
ICR0.LVLMODE = 0
⎯ Clearing IRQ interrupt requests at edge detection
⎯ Clearing IRL interrupt requests
⎯ Clearing IRQ interrupt requests at level detection
Clearing IRQ and IRL Interrupt Requests
To clear the interrupt requests IRQ7 to IRQ0 setting edge detection, read the IR7 to IR0
bits corresponding to INTREQ as 1 and write 0 to the bits. The IRQ interrupt request
being detected cannot be cleared even if 1 is written to the corresponding bit in
INTMSK0.
To clear the IRL interrupt requests from the IRQ/IRL[3:0] pins, write 1 to the IM10 bit
in INTMSK1. To clear the IRL interrupt requests from the IRQ/IRL[7:4] pins, write 1 to
the IM11 bit in INTMSK1. The IRL interrupt request being detected cannot be cleared
even if masking is performed on INTMSK2 by the level.
To clear the IRQ7 to IRQ0 interrupt request setting level detection, write 1 to the
corresponding IM07 to IM00 bits in INTMSK0. The IRQ interrupt request being
detected cannot be cleared even if 0 is written to the corresponding bit in INTPRI. The
IRQ interrupt request being detected can be checked by reading from INTREQ.
Rev.1.00 Jan. 10, 2008 Page 345 of 1658
10. Interrupt Controller (INTC)
REJ09B0261-0100