R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1142

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. Serial I/O with FIFO (SIOF)
22.3.5
SITCR is a 32-bit readable/writable register that specifies transmit control data of the SIOF. The
setting of SITCR is valid only when bits FL3 to FL0 in SIMDR are set to 1xxx (x: any value).
SITCR is initialized by the conditions shown in table 22.3, Register State in Each Operating
Mode, or by a transmit reset by the TXRST bit in SICTR.
Rev.1.00 Jan. 10, 2008 Page 1110 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 16 SITC0[15:0] H'0000
15 to 0
R/W:
R/W:
BIt:
BIt:
Transmit Control Data Register (SITCR)
Bit Name
SITC1[15:0] H'0000
R/W
R/W
31
15
—
—
R/W
R/W
30
—
14
—
R/W
R/W
29
—
13
—
Initial
Value
R/W
R/W
28
12
—
—
R/W
R/W
R/W
R/W
R/W
27
11
—
—
R/W
R/W
26
10
—
—
Control Channel 0 Transmit Data
Description
These bits specify data to be output from the
SIOF_TXD pin as control channel 0 transmit data. The
position of the control channel 0 data in the transmit or
receive frame depends on the value set in the CD0A bit
in SICDAR.
•
Control Channel 1 Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as control channel 1 transmit data. The
position of the control channel 1 data in the transmit or
receive frame depends on the CD1A bit in SICDAR.
•
R/W
R/W
25
—
—
9
These bits are valid when the CD0E bit in SICDAR
is set to 1.
These bits are valid when the CD1E bit in SICDAR
is set to 1.
SITC0[15:0]
SITC1[15:0]
R/W
R/W
24
—
—
8
R/W
R/W
23
—
—
7
R/W
R/W
22
—
—
6
R/W
R/W
21
—
—
5
R/W
R/W
20
—
—
4
R/W
R/W
19
—
—
3
R/W
R/W
18
—
—
2
R/W
R/W
17
—
—
1
R/W
R/W
16
—
—
0