R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 583

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The PCI controller (PCIC) controls the PCI bus and enables data transfers between memory
connected to an external bus and a PCI device connected to the PCI bus. The PCIC facilitates the
system design using the PCI bus and enables short and fast data transfer.
The PCIC operates as a bus bridge which links the PCI bus to the internal bus (SuperHyway bus).
It has transfer channels, for example, between a PCI device on the PCI bus and memory that is
connected to the external bus.
The PCIC supports both the host mode and normal mode (non-host mode). In host mode,
arbitration can be performed on the PCI bus. In normal mode, the PCI bus arbitration is performed
by the external PCI bus arbiter.
13.1
The PCIC has the following features.
• Conforms to the subset of the PCI Local Bus Specification Revision 2.2
• Operates at 33 or 66 MHz
• 32-bit data bus
• PCI master and target functions
• Conforms to the subset of the PCI Power Management Revision 1.1
• Supports the host mode and normal mode
• PCI arbiter (in host mode)
• Supports four external masters
• Pseudo-round-robin or fixed priority arbitration
• Supports external bus arbiter mode
• Supports configuration mechanism #1 (in host mode)
• Supports burst transfer
• Parity check and error report
• Exclusive access (only when PCIC is a target)
Exclusive access between the internal module and the external PCI master is not supported.
⎯ The PCIC is a master: Not supported
⎯ The PCIC is a target: When the PCIC is locked, it can be accessed through only the PCI
device that has asserted the LOCK signal (the SuperHyway bus is not locked during lock
transfer).
Features
Section 13 PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 551 of 1658
13. PCI Controller (PCIC)
REJ09B0261-0100