R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 368

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
Note:
Rev.1.00 Jan. 10, 2008 Page 336 of 1658
REJ09B0261-0100
Interrupt Source
HAC-ch1
FLCTL
GPIO
*
HACI1
FLSTE*
FLTEND*
FLTRQ0*
FLTRQ1*
GPIOI0 (Port E0)
GPIOI0 (Port E1)
GPIOI0 (Port E2)
GPIOI1 (Port E3)
GPIOI1 (Port E4)
GPIOI1 (Port E5)
GPIOI2 (Port H1)
GPIOI2 (Port H2)
GPIOI2 (Port H3)
GPIOI2 (Port H4)
GPIOI3 (Port L6)
GPIOI3 (Port L7)
ITI: Interval timer interrupt
TUNI0 to TUNI5: TMU channels 0 to 5 under flow interrupt
TICPI2: TMU channel 2 input capture interrupt
DMINT0 to DMINT11: Transfer end or half-end interrupts for DMAC channel 0 to 11
DMAE0: DMAC address error interrupt (channels 0 to 5)
DMAE1: DMAC address error interrupt (channels 6 to 11)
ERI0, ERI1, ERI2, ERI3, ERI4, ERI5: SCIF channels 0 to 5 receive error interrupts
RXI0, RXI1, RXI2, RXI3, RXI4, RXI5: SCIF channels 0 to 5 receive data full interrupts
BRI0, BRI1, BRI2, BRI3, BRI4, BRI5: SCIF channels 0 to 5 break interrupts
TXI0, TXI1, TXI2, TXI3, TXI4, TXI5: SCIF channels 0 to 5 transmission data empty
interrupts
FLSTE: FLCTL error interrupt
FLTEND: FLCTL error interrupt
FLTRQ0: FLCTL data FIFO transfer request interrupt
FLTRQ1: FLCTL control code FIFO transfer request interrupt
INTEVT
Code
H'EE0
H'F00
H'F20
H'F40
H'F60
H'F80
H'FA0
H'FC0
H'FE0
Interrupt
Priority
INT2PRI6
[20:16]
INT2PRI8
[28:24]
INT2PRI8
[20:16]
Mask/Clear
Register & Bit
INT2MSKR[13]
INT2MSKCLR
[13]
INT2MSKR[23]
INT2MSKCR[23]
INT2MSKR[24]
INT2MSKCR[24]
Interrupt
Source
Register
INT2A0[13]
INT2A1[13]
INT2A0[23]
INT2A1[23]
INT2A0[24]
INT2A1[24]
Detail
Source
Register
⎯
INT2B5[0]
INT2B5[1]
INT2B5[2]
INT2B5[3]
INT2B6[0]
INT2B6[1]
INT2B6[2]
INT2B6[8]
INT2B6[9]
INT2B6[10]
INT2B6[16]
INT2B6[17]
INT2B6[18]
INT2B6[19]
INT2B6[24]
INT2B6[25] Low
Priority
within
Sets of
Sources
High
Low
High
Default
Priority
High
Low