R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1388

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1356 of 1658
REJ09B0261-0100
Bit
18
17
16
15 to 9
8
Bit Name
AC0CLR
DREQ1EN 0
DREQ0EN 0
—
STERB
Initial
Value
0
All 0
0
R/W
R/W
R/W
R/W
R/W
R
Description
FLDTFIFO Clear
Clears the address counter of FLDTFIFO.
0: Retains the address counter value of FLDTFIFO. In
1: Clears the address counter of FLDTFIFO. After
FLECFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLECFIFO.
0: Disables the issue of DMA transfer request from
1: Enables the issue of DMA transfer request from
FLDTFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLDTFIFO.
0: Disables the issue of DMA transfer request from
1: Enables the issue of DMA transfer request from
Reserved
These bits are always read as 0. The write value should
always be 0.
Status Error
Indicates the result of status read. This bit is set to 1 if
the specific bit in bits STAT7 to STAT0 in FLBSYCNT is
set to 1 in status read.
Since this bit is a flag bit, 1 cannot be written to this bit.
Only 0 can be written to clear the flag.
0: Indicates that no status error occurs (the specific bit
1: Indicates that a status error occurs
For details on the specific bit, see section 27.4.4, Status
Read.
flash-memory access, clear this bit to 0.
clearing the counter, clear this bit to 0
in bits STAT7 to STAT0 in FLBSYCNT is 0.)
FLECFIFO
FLECFIFO
FLDTFIFO
FLDTFIFO