R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1511

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

29.3.6
When a break has occurred, the address of the instruction to be executed when the program
restarts is saved in the SPC then the exception handling state is initiated. A unique instruction
causing a break can be identified unless the data value is included in the match conditions.
1. When the instruction fetch cycle (before instruction execution) is specified as the match
2. When the instruction fetch cycle (after instruction execution) is specified as the match
3. When the operand access (address only) is specified as the match condition:
4. When the operand access (address and data) is specified as the match condition:
condition:
The address of the instruction which has satisfied the match conditions is saved in the SPC.
The instruction which has satisfied the match conditions is not executed, but a break occurs
instead. However, if the match conditions are satisfied for the delayed slot instruction, the
address of the delayed branch instruction is saved in the SPC.
condition:
The address of the instruction immediately after the instruction which has satisfied the match
conditions is saved in the SPC. The instruction which has satisfied the match conditions is
executed, then a break occurs before the next instruction. If the match conditions are satisfied
for the delayed branch instruction or its delayed slot, these instructions are executed and the
address of the branch destination is saved in the SPC.
The address of the instruction immediately after the instruction which has satisfied the break
conditions is saved in the SPC. The instruction which has satisfied the match conditions are
executed, then a break occurs before the next instruction. However, if the conditions are
satisfied for the delayed slot, the address of the branch destination is saved in the SPC.
If the data value is added to the match conditions, the instruction which has satisfied the match
conditions is executed. A user break occurs before executing an instruction that is one through
six instructions after the instruction which has satisfied the match conditions. The address of
the instruction is saved in the SPC; thus, it is impossible to identify exactly where a break will
occur. If the conditions are satisfied for the delayed slot instruction, the address of the branch
destination is saved in the SPC. If a branch instruction follows the instruction which has
satisfied the match conditions, a break may occur after the delayed instruction and delayed slot
are executed. In this case, the address of the branch destination is also saved in the SPC.
Program Counter Value to be Saved
Rev.1.00 Jan. 10, 2008 Page 1479 of 1658
29. User Break Controller (UBC)
REJ09B0261-0100