R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 705

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Channel Name
8
9
6 to 11
10
11
6
7
8
DMA source address register 8
DMA destination address register 8
DMA transfer count register 8
DMA channel control register 8
DMA source address register 9
DMA destination address register 9
DMA transfer count register 9
DMA channel control register 9
DMA operation register 1
DMA source address register 10
DMA destination address register 10 DAR10
DMA transfer count register 10
DMA channel control register 10
DMA source address register 11
DMA destination address register 11 DAR11
DMA transfer count register 11
DMA channel control register 11
DMA source address register B6
DMA destination address register
B6
DMA transfer count register B6
DMA source address register B7
DMA destination address register
B7
DMA transfer count register B7
DMA source address register B8
DMA destination address register
B8
DMA transfer count register B8
Abbrev.
SAR8
DAR8
TCR8
CHCR8
SAR9
DAR9
TCR9
CHCR9
DMAOR1 H'0000
SAR10
TCR10
CHCR10 H'4000 0000 H'4000 0000
SAR11
TCR11
CHCR11 H'4000 0000 H'4000 0000
SARB6
DARB6
TCRB6
SARB7
DARB7
TCRB7
SARB8
DARB8
TCRB8
Power-on
Reset
by PRESET
Pin/WDT/
H-UDI
Undefined
Undefined
Undefined
H'4000 0000 H'4000 0000
Undefined
Undefined
Undefined
H'4000 0000 H'4000 0000
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
14. Direct Memory Access Controller (DMAC)
Manual
Reset
by
WDT/Multiple
Exception
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
H'0000
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Rev.1.00 Jan. 10, 2008 Page 673 of 1658
Sleep
by SLEEP
instruction
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Deep Sleep
by SLEEP
instruction
(DSLP = 1)
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
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Retained
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Retained
REJ09B0261-0100
Module
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
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Retained