R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1181

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(6)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1
used for right-channel data, slot No.2 used for control channel 0 data, slot No.3 used for control
channel 1 data, and frame length = 128 bits
(7)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.2
used for right-channel data, slot No.1 used for control channel 0 data, slot No.3 used for control
channel 1 data, and frame length = 128 bits
SIOF_SYNC
SIOF _ SYNC
SIOF_RXD
SIOF _ RXD
SIOF_SCK
SIOF _ SCK
SIOF_TXD
SIOF _ TXD
16-bit Stereo Data (3)
16-bit Stereo Data (4)
Specifications:
Figure 22.18 Transmit and Receive Timing (16-Bit Stereo Data (3))
Figure 22.19 Transmit and Receive Timing (16-Bit Stereo Data (4))
Specifications:
Slot No.0
Slot No.0
L-channel
L-channel
1 bit delay
data
1 bit delay
data
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 1,
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 1,
Slot No.1
Slot No.1
R-channel
channel 0
Control
data
Slot No.2
Slot No.2
R-channel
channel 0
Control
data
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0010,
REDG = 1,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0001,
Slot No.3
Slot No.3
channel 1
channel 1
Control
Control
1 frame
1 frame
Slot No.4
Slot No.4
FL[3:0] = 1110 (frame length: 128 bits),
TDRE = 1,
RDRE = 1,
CD1E = 1,
FL[3:0] = 1110 (frame length: 128 bits)
TDRE = 1,
RDRE = 1,
CD1E = 1,
Rev.1.00 Jan. 10, 2008 Page 1149 of 1658
Slot No.5
Slot No.5
TDRA[3:0] = 0001,
RDRA[3:0] = 0001,
CD1A[3:0] = 0011
22. Serial I/O with FIFO (SIOF)
TDRA[3:0] = 0010,
RDRA[3:0] = 0010,
CD1A[3:0] = 0011
Slot No.6
Slot No.6
Slot No.7
REJ09B0261-0100
Slot No.7
SYNCDL = 1
SYNCDL = 1