R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1230

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24. Multimedia Card Interface (MMCIF)
24.3.12 Response Type Register (RSPTYR)
RSPTYR is an 8-bit readable/writable register that specifies command format in conjunction with
CMDTYR. Bits RTY2 to RTY0 specify the number of response bytes, and bits RTY6 to RTY4
specify the additional settings.
Rev.1.00 Jan. 10, 2008 Page 1198 of 1658
REJ09B0261-0100
Bit
3
2
1
0
Bit
7
Bit Name
TY3
TY2
TY1
TY0
Bit Name
⎯
Initial value:
Initial
Value
0
0
0
0
Initial
Value
0
R/W:
Bit:
⎯
R
7
0
R/W
R/W
R/W
R/W
R/W
R/W
R
RTY6
R/W
6
0
Description
Type 3
Set this bit to 1 when specifying stream transfer. Bits
TY1 and TY0 should be set to 01 or 10.
The command sequence of the stream transfer
specified by this bit ends when it is aborted by the
CMD12 command.
Type 2
Set this bit to 1 when specifying a multiple block
transfer. Bits TY1 and TY0 should be set to 01 or 10.
The command sequence of the multiple block transfer
specified by this bit ends when it is aborted by the
CMD12 command.
Types 1 and 0
These bits specify the existence and direction of
transfer data.
00: A command without data transfer
01: A command with read data reception
10: A command with write data transmission
11: Setting prohibited
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
RTY5 RTY4
R/W
5
0
R/W
4
0
⎯
R
0
3
RTY2 RTY1 RTY0
R/W
2
0
R/W
1
0
R/W
0
0