R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 401
![IC SUPERH MPU ROMLESS 436-BGA](/photos/28/62/286211/436-bfbga_sml.jpg)
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 401 of 1694
- Download datasheet (9Mb)
Bit
19, 18
17
16
15
14
13 to 7
Bit Name
⎯
BREQEN
DMABST
⎯
HIZCNT
⎯
Initial
Value
All 0
0
0
0
0
All 0
R/W
R
R/W
R/W
R
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
BREQ Enable
Specifies whether an external request can be accepted
or not. In the initialized state at a power-on reset, an
external request is not accepted. When this LSI is
booted up in slave mode, an external request is
accepted regardless of the BREQEN value.
0: An external request is not accepted
1: An external request is accepted
DMAC Burst Mode Transfer Priority Setting
Specifies the priority of burst mode transfers by DMA
channels 0 to 5. When this bit is cleared to 0, the
priority is as follows: bus release, DMAC (burst mode),
CPU, DMAC, PCIC. When this bit is set to 1, the bus is
not released until completion of the DMAC burst
transfer. This bit is initialized at a power-on reset.
0: DMAC burst mode transfer priority setting is off
1: DMAC burst mode transfer priority setting is on
Reserved
This bit is always read as 0. The write value should
always be 0.
High Impedance (Hi-Z) Control
Specifies the state of signals WEn and RD/FRAME in
the bus-released state.
0: Signals WEn and RD/FRAME are high-impedance in
1: Signals WEn and RD/FRAME are driven in the bus-
Reserved
These bits are always read as 0. The write value should
always be 0.
the bus-released state
released state
Rev.1.00 Jan. 10, 2008 Page 369 of 1658
11. Local Bus State Controller (LBSC)
REJ09B0261-0100
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