R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 699

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.2
The DMAC-related external pins are shown below.
Table 14.1 shows the configuration of the pins that are connected to external device. The DMAC
has pins for four channels (channels 0 to 3) used in the external bus.
Table 14.1 Pin Configuration for the External Bus
Notes: 1. The initial value is low-level detection.
Channel Function
0
1
2
3
2. The initial value is low-active.
Input/Output Pins
DMA transfer request
DREQ0 acceptance
confirmation
DMA transfer end
notification
DMA transfer request
DREQ1 acceptance
confirmation
DMA transfer end
notification
DMA transfer request
DREQ2 acceptance
confirmation
DMA transfer end
notification
DMA transfer request
DREQ3 acceptance
confirmation
DMA transfer end
notification
Pin Name I/O
DREQ0*
DRAK0*
DACK0*
DREQ1*
DRAK1*
DACK1*
DREQ2*
DRAK2*
DACK2*
DREQ3*
DRAK3*
DACK3*
2
2
2
2
2
2
2
2
1
1
1
1
Input
Output Notifies acceptance of DMA transfer
Output Outputs strobe to DMA transfer request
Input
Output Notifies acceptance of DMA transfer
Output Outputs strobe to DMA transfer request
Input
Output Notifies acceptance of DMA transfer
Output Outputs strobe to DMA transfer request
Input
Output Notifies acceptance of DMA transfer
Output Outputs strobe to DMA transfer request
Description
DMA transfer request input from external
device to channel 0
request and start of execution from
channel 0 to external device
from channel 0 to external device
DMA transfer request input from external
device to channel 1
request and start of execution from
channel 1 to external device
from channel 1 to external device
DMA transfer request input from external
device to channel 2
request and start of execution from
channel 2 to external device
from channel 2 to external device
DMA transfer request input from external
device to channel 3
request and start of execution from
channel 3 to external device.
from channel 3 to external device
14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 667 of 1658
REJ09B0261-0100