R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1500
R8A77850ANBGV
Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77850AADBGV.pdf
(1694 pages)
Specifications of R8A77850ANBGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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29. User Break Controller (UBC)
29.2.5
CDR1 is a readable/writable 32-bit register which specifies the data value to be included in the
break conditions for channel 1.
Table 29.3 Settings for Match Data Setting Register
Notes: 1. If the data value is included in the match conditions, be sure to specify the operand
Rev.1.00 Jan. 10, 2008 Page 1468 of 1658
REJ09B0261-0100
Bit
31 to 0
Bus and Size Selected
Using CBR1
Operand bus (byte)
Operand bus (word)
Operand bus (longword) SDB31 to SDB24 SDB23 to SDB16 SDB15 to SDB8 SDB7 to SDB0
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
2. The OCBI instruction is handled as longword write access without the data value, and
3. If the quadword access is specified and the data value is included in the match
Match Data Setting Register 1 (CDR1)
Bit Name
CD
size.
the PREF, OCBP, and OCBWB instructions are handled as longword read access
without the data value. Therefore, do not include the data value in the match conditions
for these instructions.
conditions, the upper and lower 32 bits of 64-bit data are each compared with the
contents of both the match data setting register and match data mask setting register.
R/W
R/W
31
15
R/W
R/W
30
14
R/W
R/W
Initial
Value
Undefined
29
13
CD[31:24]
Don't care
Don't care
R/W
R/W
28
12
R/W
R/W
27
11
R/W
R/W
R/W
R/W
26
10
Description
Compare Data Value
Specifies the data value to be included in the break
conditions.
When the operand bus has been specified using the
CBR1 register, specify the SDB data value in CD[31:0].
CD[23:16]
Don't care
Don't care
R/W
R/W
25
9
R/W
R/W
24
8
CD
CD
R/W
R/W
23
7
R/W
R/W
22
6
CD[15:8]
Don't care
SDB15 to SDB8 SDB7 to SDB0
R/W
R/W
21
5
R/W
R/W
20
4
R/W
R/W
19
3
CD[7:0]
SDB7 to SDB0
R/W
R/W
18
2
R/W
R/W
17
1
R/W
R/W
16
0
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